1. Field of the Invention
This invention relates to a non-volatile memory device, and more particularly to a readout system circuit of a non-volatile memory device.
2. Description of the Related Art
A flash type EEPROM (Electrically Erasable Programmable Read Only Memory) is one type of electrically erasable and programmable non-volatile memory. Each memory cell of such a non-volatile memory can be constructed by one transistor unlike a two-transistor type byte type non-volatile semiconductor memory. Therefore, the memory cell size can be reduced and it is expected to use this type of memory instead of a magnetic disk of large capacity.
The construction of a memory cell constructed by a floating gate MOS transistor in the flash type EEPROM and general data programming and erasing means are explained with reference to FIGS. 1 and 2.
FIG. 1 is a plan view of a memory cell portion of the floating gate MOS transistor and FIG. 2 is a cross sectional view taken along the line 2--2 of FIG. 1. The floating gate MOS transistor has a stacked gate electrode 56 which is constructed by a gate oxide film 52 formed on a semiconductor substrate 51, a floating gate 53 of polysilicon formed on the gate oxide film, a gate oxide film 54 formed on the floating gate, and a control gate 55 of polysilicon formed on the gate oxide film. A source region 57 and a drain region 58 are formed in the surface area of the substrate 51 by implanting ions into the substrate surface with the gate electrode 56 used as a mask.
Generally, the data programming operation is effected by applying a voltage of 6 to 7 V to the drain region and applying a high voltage of approx. 12 V to the control gate 55. In this operation, the floating gate 53 is set to a high potential because of the capacitive coupling, thereby causing hot electrons generated by the avalanche breakdown in a portion near the drain region to be injected into the floating gate 53 via the gate oxide film 52. As a result, the threshold voltage of the memory cell is enhanced and the programming operation is completed.
Further, in the erasing operation, the control gate 55 is set to the ground potential, the drain region 58 is set in the electrically open state, and a high voltage is applied to the source region 57 to discharge electrons injected into the floating gate 53 by a method called the Fowler-Nordheim tunneling so as to lower the threshold voltage of the memory cell. In order to achieve the above programming and erasing operations, the oxide film 52 lying under the floating gate 53 is formed of a thin oxide film called a tunnel oxide film.
FIG. 3 is a circuit diagram showing the construction of a readout system circuit in the conventional flash type EEPROM. A memory cell MC is one of non-volatile transistors constituting a memory cell array 11, the control gate thereof is connected to a word line WL which is supplied with a row address signal via a row decoder 12, the source thereof is connected to GND (ground potential), and the drain thereof is connected to a bit line BL. The bit line BL is connected to a sense amplifier 15 via a column gate 14 which receives a column address signal from a column decoder 13 at the gate thereof.
The bit line BL is connected to a pre-amplifier circuit PR1 in the sense amplifier 15. For example, the pre-amplifier PR1 is constructed by a transistor which receives an intermediate bias voltage Vbias at the gate thereof and supplies a low voltage of approx. 1 V to the bit line BL. An output line 16 connected to the bit line BL via the pre-amplifier PR1 is connected to the inverting input terminal of a differential amplifier AMP via a load TR1. The load TR1 is a P-channel transistor whose gate and drain are connected to the output line and whose source is connected to a high potential side power source, for example.
The non-inverting input terminal of the differential amplifier AMP is connected to a dummy cell side output line used as a reference. The control gate, source and drain of a dummy cell DMC are respectively connected to a power supply potential VC, GND and a dummy bit line DBL. The dummy bit line DBL is connected to a pre-amplifier circuit PR2 having the same construction as the above pre-amplifier circuit via a transistor having the same construction as the above column selection transistor. An output line connected to the bit line DBL via the pre-amplifier PR2 is connected to the non-inverting input terminal of the differential amplifier AMP via a load TR2. The weight of the load TR2 is set twice that of the load TR1, for example.
The readout operation of the circuit with the above construction is as follows. In order to determine whether a memory cell MC selected by signals generated from the row decoder and column decoder in response to an input address signal, a variation in the potential of the bit line BL is detected by the differential amplifier AMP. That is, programming data of "0" from the exterior is stored as the OFF state by storing electrons into the floating gate. This is called an "OFF" cell. In the case of "1" data, electrons are not stored and data is stored as the ON state. This is called an "ON" cell.
The dummy cell DMC on the reference side is set in the normally-ON state and an input voltage Vref from the dummy cell side in the differential amplifier AMP is determined based on the relation between the current Idcel of the dummy cell and the load TR2. The voltage Vref is a preset intermediate potential and is set to a potential between an input potential to the inverting input terminal set when the selected memory cell is an ON cell and an input potential to the inverting input terminal set when the selected memory cell is an OFF cell.
That is, as shown in FIG. 4, the input potential Vsa of the differential amplifier AMP from the cell side is set to a potential Vsa lower than the intermediate potential vref by the weighting of the loads when the memory cell MC is set in the ON state. Therefore, the output OUT of the sense amplifier S/A is set to the "H" level and the selected memory cell is determined to be an ON cell. Further, since no DC path to GND is provided when the selected memory cell MC is set in the OFF state, the potential Vsa is pulled up to a level higher than the intermediate potential vref. Therefore, the detection output of the sense amplifier is set to the "L" level and the selected memory cell is determined to be an OFF cell.
With the above construction, a certain potential is applied to a bit line connected to a selected column decoder irrespective of ON/OFF of the cell. The potential is controlled to approx. 1 V irrespective of ON/OFF of the cell in the actual circuit by taking the reliability of the cell into consideration.
However, since the memory cell size tends to be reduced in order to attain a larger memory capacity, the channel length thereof is reduced, hot electrons tend to be generated and the reliability for the drain voltage is made severe. Further, the tunnel oxide film formed under the floating gate for erasing permits a tunnel current to easily flow when the gate electric field is applied and the reliability for the gate voltage is severe.
A voltage of 5 V is applied to a cell connected to a selected row decoder. The drain voltage is 1 V and the gate voltage is 5 v at the readout time. The voltage stresses will not cause any problem in a short period of time. However, in order to provide the warranty for 10 to 20 years, they may be an important problem from the viewpoint of further improvement of the reliability.
At present, the reliability required for the memory cell subject to the above stresses are satisfied from the viewpoint of process and structure, and they are mass-produced. However, in order to further enhance the reliability, it is important to pay more attention to the circuit design.
The point to be noted is that the stress is always applied to any one of the cells irrespective of the readout at the time of CE (chip enable) in the prior art. Further, the voltage stress is applied to a specified cell in many cases in the standby mode of the chip. Therefore, it is necessary to design the circuit structure so as to solve the above problem.